1. Field of the Invention
The present invention relates to the field of accessing data during data processing.
2. Description of the Prior Art
Data processors typically store data in a number of different places, which generally include memory regions and at least one cache. The memory regions can be formed of different types of memory, but in general they are relatively cheap and therefore can be large but they are not quick to access. Caches on the other hand generally comprise faster data storage and are therefore more expensive but are quicker to access. Thus, in order to improve the performance of a data processor, and in particular data accesses within the processor, data that is to be accessed a number of times may be copied from memory to a cache. Then in response to a data access request the processor will generally look to see if the data is in the cache first, and only if it is not there and a cache miss occurs, will it look further at other memory.
FIG. 1 shows a flow diagram showing a standard mechanism for requesting external memory according to the prior art. A memory request is delivered from the instruction pipeline of the processor and in response to this, the processor looks in the cache for the piece of data requested (read cache memory). If there is a cache hit detection, then the data is returned to the pipeline, i.e. the “yes” line is followed. If there is no cache hit detection, then the processor follows the “no” line and proceeds to request an external memory access and perform this external memory access to retrieve the data.
As access to memory is much more time consuming than access to a cache is, improvements to the performance of data processors, with regard to data access, are generally concerned with providing more cache and improving cache access.